1. Field of the Invention
The present invention relates to a variable gain amplifier, and in particular to a variable gain amplifier controlling a gain with a differential amplifier by a gain control signal.
The variable gain amplifier is utilized in many devices using electric circuits regardless of technical fields. When an extension of an input dynamic range is intended for the sake of circuit designs, it is required to be used not only as a simple variable gain amplifier but also, for instance, as a linear amplifier for a small signal input, as a variable gain amplifier for a middle signal input or as an amplitude limiting amplifier for a large signal input.
2. Description of the Related Art
FIG. 14 shows an arrangement of a conventional variable gain amplifier. This variable gain amplifier is composed of two differential amplifiers Q1 and Q2 sharing load resistors R1 and R2, a differential amplifier Q3 to perform a gain switchover of the differential amplifiers Q1 and Q2, and a bias current source B1 to provide a bias current to the differential amplifiers Q1 and Q2 through the differential amplifier Q3.
In comparison under the same bias current amount, the differential amplifier Q1 provides a higher gain than the differential amplifier Q2. The drains of transistors M3 and M5 which respectively compose a high and a low gain differential amplifier Q1 and Q2 are mutually coupled and commonly connected to the load resistor R1. Similarly, the drains of transistors M4 and M6 are mutually coupled and commonly connected to the load resistor R2.
Also, the sources of the transistors M3 and M4 in the gain differential amplifier Q1 are mutually coupled and commonly connected to the drain of a transistor M1 which composes the gain switchover differential amplifier Q3. In the same way, the sources of the transistors M5 and M6 in the low gain differential amplifier Q2 are mutually coupled and commonly connected to the drain of a transistor M2 which composes the differential amplifier Q3.
Furthermore, the gates of the transistors M3 and M5 are commonly connected to a signal input terminal S1. Similarly, the gates of the transistors M4 and M6 are commonly connected to a signal input terminal S2. Junctions of the differential amplifiers Q1, Q2 and the load resistors R1, R2 are connected to output terminals O1 and O2, respectively.
In addition, the sources of the transistors M1 and M2 in the gain switchover differential amplifier Q3 are mutually coupled and commonly connected to the bias current source B1, the gate terminal of the transistor M1 is connected to a gain control signal input terminal C1, and the gate of the transistor M2 is connected to a gain control signal input terminal C2.
In such a variable gain amplifier, the ratio (1-.alpha.): .alpha. [0.ltoreq..alpha..ltoreq.1] of current amounts which flows through the high and the low gain differential amplifier Q1 and Q2 is controlled by varying the voltage of the gain control signal given from the signal input terminals C1 and C2 to the gates of the transistors M1 and M2 in the gain switchover differential amplifier Q3, so that the output gain is made variable by keeping constant a DC (direct current) amount which flows through the load resistors R1 and R2 without varying a DC level outputted to the output terminals O1 and O2 determined by a load resistance X the DC amount.
Namely, each small signal gain G of the CMOS differential amplifiers Q1 and Q2 where each load resistance of the load resistors R1 and R2 is R1 is expressed, by using a mutual conductance g.sub.m, as G=g.sub.m .times.Rl. Since g.sub.m is proportional to the root of a bias current I.sub.s by the current source B1, G=Rl.times.kI.sub.s.sup.0.5 is given where k is a coefficient depending on a size .beta. of a transistor.
From this, a small signal gain Gv is given by the following equation as a variable gain amplifier whose gain varies with the bias current ratio .alpha., which is a value controlled by the input potential of the differential amplifier Q3, of the differential amplifiers Q1 and Q2 shown in FIG. 14: EQU Gv=Rl{kh[(1-.alpha.)Is].sup.0.5 +kl[.alpha.Is].sup.0.5 } Eq. (1)
where subscripts h and l indicate that they are attendant on the high and the low gain differential amplifier.
In Eq. (1), the first and the second term in the right member { } respectively indicate gain variations of the high and the low gain differential amplifier Q1 and Q2 for the current ratio .alpha. as shown by symbols .circle-solid. and .tangle-solidup. in FIG. 15. The characteristic of the small signal gain Gv in the variable gain amplifier where both symbols are compounded is shown by a symbol .box-solid. in FIG. 15.
It is seen from the gain characteristic shown in FIG. 15 that while .alpha. varies from 0, the small signal gain Gv does not monotonously decrease but the gain once expands as shown by an enclosed part with a dotted line 100.
This is because the gain variations of resistance load type differential amplifiers Q1 and Q2 are not linear around 0 of the bias current ratio a where only the high gain differential amplifier Q1 operates, and the gain rises of the transistors M5 and M6 in the low gain differential amplifier Q2 are larger than the gain falls of the transistors M3 and M4 in the high gain differential amplifier Q1.
Accordingly, the gain variation is not monotonous for the variation of the bias current ratio .alpha., i.e. the variation of the gain control signal input, so that when the gain fall is required, the gain will rise, resulting in a possibility of malfunction.
On the other hand, the manufacture of transistors with a lower cost by using a big diameter wafer has become popular by improved minute machining techniques for the transistors in recent years, while an available power source voltage have a tendency to decrease as the transistors are more minutely machined.
However, in the above-mentioned variable gain amplifier, the high or the low gain differential amplifier, the gain switchover differential amplifier and the bias current source are connected in series across current source terminals. Therefore, it is disadvantageous that as the number of transistors connected in cascade increases, a sufficient operation voltage is not secured and a DC design becomes difficult.